GFIFOPRIDBC (USB3_XHCI) Register Description
| Register Name | GFIFOPRIDBC |
|---|---|
| Offset Address | 0x000000C620 |
| Absolute Address |
0x00FE20C620 (USB3_0_XHCI) 0x00FE30C620 (USB3_1_XHCI) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | Global Host Debug Capability DMA Priority Register This register specifies the relative priority of the RXFIFOs and TXFIFOs associated with the DbC mode. It overrides the priority assigned in the corresponding indexes of the Host RXFIFO and TXFIFO DMA priority registers, when the DbC mode is enabled. Priority settings are specified in relation to the low-priority SS speed group: - 1. Normal priority indicates that the DbC FIFOs are considered identical to the Host SS low-priority FIFOs. - 2. Low priority indicates that the DbC FIFOs are considered to have lower priority than all Host SS FIFOs. - 3. High priority indicates that the DbC FIFOs are considered higher priority than the Host SS low-priority FIFOs but lower priority than the Host SS high-priority FIFOs. This register is present only when the core is configured to operate in Host Debug Capability (DbC) mode. |
GFIFOPRIDBC (USB3_XHCI) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:2 | roRead-only | 0x0 | Reserved |
| gfifopridbc | 1:0 | rwNormal read/write | 0 | Host DbC DMA priority |