FEAT1R (STM) Register Description
| Register Name | FEAT1R |
|---|---|
| Offset Address | 0x0000000EA0 |
| Absolute Address | 0x00FE9C0EA0 (CORESIGHT_SOC_STM) |
| Width | 32 |
| Type | roRead-only |
| Reset Value | 0x00000000 |
| Description | Read the features of the STM. |
FEAT1R (STM) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| SWOEN | 23:22 | roRead-only | 0x0 | STMTCSR.SWOEN support: 1: not implemented. |
| SYNCEN | 21:20 | roRead-only | 0x0 | STMTCSR.SYNCEN support: 2: RAO. |
| HWTEN | 19:18 | roRead-only | 0x0 | STMTCSR.HWTEN support: 1: not implemented. |
| TSPRESCALE | 17:16 | roRead-only | 0x0 | Timestamp prescale support: 1: not implemented. |
| TRIGCTL | 15:14 | roRead-only | 0x0 | Trigger control support. |
| TRACEBUS | 13:10 | roRead-only | 0x0 | Trace bus support: 1: ATB with trigger. |
| SYNC | 9:8 | roRead-only | 0x0 | STMSYNCR support: 3: mode. |
| FORCETS | 7 | roRead-only | 0x0 | STMTSSTIMR support: 1: implemented. |
| TSFREQ | 6 | roRead-only | 0x0 | Timestamp frequency indication configuration: 1: RW. |
| TS | 5:4 | roRead-only | 0x0 | Timestamp support: 1: absolute. |
| PROT | 3:0 | roRead-only | 0x0 | Protocol: 1: STPv2. |