Intrpt_en (UART) Register Description
| Register Name | Intrpt_en |
|---|---|
| Offset Address | 0x0000000008 |
| Absolute Address |
0x00FF000008 (UART0) 0x00FF010008 (UART1) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | Interrupt Enable Register |
This write only register is used to enable interrupts. When any bit is written high, the corresponding interrupt is enabled. Writing a low to any bit has no effect.
Intrpt_en (UART) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:14 | roRead-only | 0x0 | Reserved, read as zero, ignored on write. |
| RBRK | 13 | woWrite-only | 0x0 | Receiver break detect interrupt: 0: no effect 1: When set to 1, the Receiver break detect interrupt is enabled (clears mask = 0) |
| TOVR | 12 | woWrite-only | 0x0 | Transmitter FIFO Overflow interrupt: 0: no effect 1: enable (clears mask = 0) |
| TNFUL | 11 | woWrite-only | 0x0 | Transmitter FIFO Nearly Full interrupt: 0: no effect 1: enable (clears mask = 0) |
| TTRIG | 10 | woWrite-only | 0x0 | Transmitter FIFO Trigger interrupt: 0: disable 1: enable |
| DMSI | 9 | woWrite-only | 0x0 | Delta Modem Status Indicator interrupt: 0: no effect 1: enable (clears mask = 0) |
| TIMEOUT | 8 | woWrite-only | 0x0 | Receiver Timeout Error interrupt: 0: no effect 1: enable (clears mask = 0) |
| PARE | 7 | woWrite-only | 0x0 | Receiver Parity Error interrupt: 0: disable 1: enable |
| FRAME | 6 | woWrite-only | 0x0 | Receiver Framing Error interrupt: 0: no effect 1: enable (clears mask = 0) |
| ROVR | 5 | woWrite-only | 0x0 | Receiver Overflow Error interrupt: 0: no effect 1: enable (clears mask = 0) |
| TFUL | 4 | woWrite-only | 0x0 | Transmitter FIFO Full interrupt: 0: no effect 1: enable (clears mask = 0) |
| TEMPTY | 3 | woWrite-only | 0x0 | Transmitter FIFO Empty interrupt: 0: disable 1: enable |
| RFUL | 2 | woWrite-only | 0x0 | Receiver FIFO Full interrupt: 0: no effect 1: enable (clears mask = 0) |
| REMPTY | 1 | woWrite-only | 0x0 | Receiver FIFO Empty interrupt: 0: no effect 1: enable (clears mask = 0) |
| RTRIG | 0 | woWrite-only | 0x0 | Receiver FIFO Trigger interrupt: 0: no effect 1: enable (clears mask = 0) |