SMMU_NSTLBGSYNC (SMMU500) Register - UG1087

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

SMMU_NSTLBGSYNC (SMMU500) Register Description

Register NameSMMU_NSTLBGSYNC
Offset Address0x0000000470
Absolute Address 0x00FD800470 (SMMU_GPV)
Width32
TypewoWrite-only
Reset Value0x00000000
DescriptionStarts a global synchronization operation that ensures the completion of any previously accepted TLB Invalidate operation. As a minimum, the operation applies to the specified security state, and includes all TLB Invalidate operations initiated in context banks associated with that security state.

SMMU_NSTLBGSYNC (SMMU500) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
bits31:0woWrite-only0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details