PP0_WB0_TARGET_FLAGS (GPU) Register Description
| Register Name | PP0_WB0_TARGET_FLAGS |
|---|---|
| Offset Address | 0x0000008118 |
| Absolute Address | 0x00FD4B8118 (GPU) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | WB0 Target Flags Register |
PP0_WB0_TARGET_FLAGS (GPU) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| _ | 31:6 | rwNormal read/write | 0x0 | Reserved, write as zero, read undefined. |
| WB0_BIG_ENDIAN | 5 | rwNormal read/write | 0x0 | When enabled, pixels are written in big-endian byte order. When disabled, pixels are written in little-endian byte order. |
| WB0_DITHER_ENABLE | 4 | rwNormal read/write | 0x0 | When enabled, dithering of the write-back data is performed using Bayer ordered dithering. Dithering is only possible when FP_TILEBUF_ENABLE is off. Note: Dithering only is supported when the tilebuffer is not downsampled more than a factor of four in either dimension, that is, the tilebuffer size is not less than 4x4 pixels. |
| WB0_INV_COMPONENT_ORDER_ENABLE | 3 | rwNormal read/write | 0x0 | When enabled, color formats get the order of their components inverted, for example: RGBA -> ARGB. This, together with WB0_SWAP_RED_BLUE_ENABLE makes it possible to support different component permutations of WB0_TARGET_PIXEL_FORMAT. |
| WB0_SWAP_RED_BLUE_ENABLE | 2 | rwNormal read/write | 0x0 | When enabled, color formats get their red and blue components swapped, for example: RGBA->BGRA. This, together with WB0_INV_COMPONENT_ORDER_ENABLE makes it possible to support different component permutations of WB0_TARGET_PIXEL_FORMAT. |
| WB0_BOUNDING_BOX_ENABLE | 1 | rwNormal read/write | 0x0 | When enabled, write-back is limited to inside the rectangular box defined by the BOUNDING_BOX_LEFT_RIGHT and BOUNDING_BOX_BOTTOM registers. |
| WB0_DIRTY_BIT_ENABLE | 0 | rwNormal read/write | 0x0 | When enabled, only pixels written to in the tile buffer are written back to the framebuffer. |