SMMU_SMR4 (SMMU500) Register Description
| Register Name | SMMU_SMR4 |
|---|---|
| Offset Address | 0x0000000810 |
| Absolute Address | 0x00FD800810 (SMMU_GPV) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | Matches a transaction with a particular Stream mapping register group. |
SMMU_SMR4 (SMMU500) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| VALID | 31 | rwNormal read/write | 0x0 | Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details |
| MASK | 30:16 | rwNormal read/write | 0 | Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details |
| ID | 14:0 | rwNormal read/write | 0 | Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details |