DDR_CNTRL (PMU_GLOBAL) Register Description
| Register Name | DDR_CNTRL |
|---|---|
| Offset Address | 0x0000000070 |
| Absolute Address | 0x00FFD80070 (PMU_GLOBAL) |
| Width | 1 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | DDR Output Signal Latch Control. |
Register is reset only by a POR reset.
DDR_CNTRL (PMU_GLOBAL) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| RET | 0 | rwNormal read/write | 0x0 | Signal Output Retention Control. Write sequence operation. Transition 0 to 1: latch DDR outputs to current state. Transition 1 to 0: allow DDR controller to control outputs. Transitions 0 to 0 and 1 to 1 have no effect. The PMU firmware can hold the state of the DDR output buffers while the DDR controller is powered-down. |