GLOBAL_RESET (PMU_GLOBAL) Register Description
| Register Name | GLOBAL_RESET |
|---|---|
| Offset Address | 0x0000000608 |
| Absolute Address | 0x00FFD80608 (PMU_GLOBAL) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | GLOBAL_RESET |
GLOBAL_RESET (PMU_GLOBAL) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:11 | roRead-only | 0x0 | reserved |
| PS_ONLY_RST | 10 | rwNormal read/write | 0x0 | The PS can be reset by itself by clearing [Prog_Gate] and using [PS_ONLY_RST] to initiate the reset. 0: reset released to PS. 1: PS held in reset. Refer to PMU_GLOBAL.PS_CNTRL [Prog_Gate] for more information on blocking the reset from propagating to the entire device. |
| FPD_RST | 9 | rwNormal read/write | 0x0 | FPD Reset to APUs, DDR memory Controller, AXI, etc. 0: reset released to FPD. 1: FPD held in reset. Note: this reset should be used to reset the DDR memory controller. |
| RPU_LS_RST | 8 | rwNormal read/write | 0x0 | RPU Lockstep Reset. Split Mode: 0: reset released to RPU0. 1: RPU0 held in reset. RPU Lockstep Mode: 0: reset released to RPU{0, 1}. 1: RPU{0, 1} held in reset. |
| Reserved | 7:0 | roRead-only | 0x0 | reserved |