ATTR_37 (PCIE_ATTRIB) Register Description
| Register Name | ATTR_37 |
|---|---|
| Offset Address | 0x0000000094 |
| Absolute Address | 0x00FD480094 (PCIE_ATTRIB) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x000049FF |
| Description | ATTR_37 |
This register should only be written to during reset of the PCIe block
ATTR_37 (PCIE_ATTRIB) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| attr_link_cap_rsvd_23 | 15 | rwNormal read/write | 0x0 | Reserved bit in Link Capability register |
| attr_link_cap_aspm_optionality | 14 | rwNormal read/write | 0x1 | Sets the ASPM Optionality Compliance bit, to comply with the 2.1 ASPM Optionality ECN. Transferred to the Link Capabilities register. |
| attr_link_cap_max_link_speed | 13:10 | rwNormal read/write | 0x2 | Maximum Link Speed. Valid settings are: 0001b [2.5 GT/s], 0010b [5.0 GT/s and 2.5 GT/s]. |
| attr_link_cap_link_bandwidth_notification_cap | 9 | rwNormal read/write | 0x0 | Link Bandwidth notification capability. Indicates support for the link bandwidth notification status and interrupt mechanism. Required for Root. |
| attr_link_cap_l1_exit_latency_gen2 | 8:6 | rwNormal read/write | 0x7 | Sets the exit latency from L1 state to be applied (at 5G) where separate clocks are used. Transferred to the Link Capabilities register. |
| attr_link_cap_l1_exit_latency_gen1 | 5:3 | rwNormal read/write | 0x7 | Sets the exit latency from L1 state to be applied (at 2.5G) where separate clocks are used. Transferred to the Link Capabilities register. |
| attr_link_cap_l1_exit_latency_comclk_gen2 | 2:0 | rwNormal read/write | 0x7 | Sets the exit latency from L1 state to be applied (at 5G) where a common clock is used. Transferred to the Link Capabilities register. |