Interrupt_Status_Enable_Register (NAND) Register Description
| Register Name | Interrupt_Status_Enable_Register |
|---|---|
| Offset Address | 0x0000000014 |
| Absolute Address | 0x00FF100014 (NAND) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | Interrupt Status Enable. |
0: disable. 1: enable.
Interrupt_Status_Enable_Register (NAND) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:8 | razRead as zero | 0x0 | reserved |
| error_ahb_sts_en | 7 | rwNormal read/write | 0x0 | AHB Error Interrupt. This is applicable only during MDMA mode of transfer. |
| dma_int_sts_en | 6 | rwNormal read/write | 0x0 | DMA Interrupt. This is applicable only during MDMA mode of transfer. |
| ecc_err_intrpt_sts_en | 5 | rwNormal read/write | 0x0 | ECC error Interrupt, in SLC (Hamming). |
| err_intrpt_sts_en | 4 | rwNormal read/write | 0x0 | Single bit error Interrupt for SLC and MLC. |
| mul_bit_err_sts_en | 3 | rwNormal read/write | 0x0 | Multi-bit error Interrupt. This field is used during Hamming (SLC) Error correction else treated as 0. |
| trans_comp_sts_en | 2 | rwNormal read/write | 0x0 | Transfer Complete Interrupt. |
| buff_rd_rdy_sts_en | 1 | rwNormal read/write | 0x0 | Buffer Read Ready Interrupt. |
| buff_wr_rdy_sts_en | 0 | rwNormal read/write | 0x0 | Buffer write Ready Interrupt. |