L0_TX_ANA_TM_117 (SERDES) Register Description
| Register Name | L0_TX_ANA_TM_117 |
|---|---|
| Offset Address | 0x00000001D4 |
| Absolute Address | 0x00FD4001D4 (SERDES) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | Register value is generated by Vivado PCW. |
L0_TX_ANA_TM_117 (SERDES) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| TX_ANA_TM_117_31_8_rsvd | 31:8 | roRead-only | 0x0 | Value generated by PCW. |
| multilane_byp1_7_6_rsvd | 7:6 | roRead-only | 0x0 | Value generated by PCW. |
| TX_pcie_4x_cfg_en | 5 | rwNormal read/write | 0x0 | Value generated by PCW. |
| force_TX_pcie_4x_cfg_en | 4 | rwNormal read/write | 0x0 | Value generated by PCW. |
| TX_pcie_2x_cfg_en | 3 | rwNormal read/write | 0x0 | Value generated by PCW. |
| force_TX_pcie_2x_cfg_en | 2 | rwNormal read/write | 0x0 | Value generated by PCW. |
| TX_dp_multilane_cfg_en | 1 | rwNormal read/write | 0x0 | Value generated by PCW. |
| force_TX_dp_multilane_cfg_en | 0 | rwNormal read/write | 0x0 | Value generated by PCW. |