CONTROL (RTC) Register Description
| Register Name | CONTROL |
|---|---|
| Offset Address | 0x0000000040 |
| Absolute Address | 0x00FFA60040 (RTC) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x01000000 |
| Description | Control. |
CONTROL (RTC) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Battery_Enable | 31 | woWrite-only | 0x0 | Enables the RTC. By writing a 0 to this bit, RTC will be powered off and the only module that potentially draws current from the battery will be BBRAM. The value read through this bit does not necessarily reflect whether RTC is enabled or not. It is expected that RTC is enabled every time it is being configured. If RTC is not used in the design, FSBL will disable it by writing a 0 to this bit. 0: RTC power off. 1: RTC power on. Read-only. |
| Reserved | 30:28 | rwNormal read/write | 0x0 | Reserved |
| Osc_Cntrl | 27:24 | rwNormal read/write | 0x1 | Bit 24: Crystal Enable Bit 25: Crystal Test Enable Bits [27:26]: Reserved |
| Reserved | 23:1 | rwNormal read/write | 0x0 | Reserved |
| SLVERR_Enable | 0 | rwNormal read/write | 0x0 | Enables SLVERR (Slave Error) if there is an access to an invalid register address. By default, this feature is disabled. 0: SLVERR is disabled. Writes are ignored and Reads return 0. 1: SLVERR is enabled. SLVERR is asserted. Writes are ignored and Reads return 0. |