MIO_PIN_26 (IOU_SLCR) Register Description
| Register Name | MIO_PIN_26 |
|---|---|
| Offset Address | 0x0000000068 |
| Absolute Address | 0x00FF180068 (IOU_SLCR) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | MIO Device Pin 26 Multiplexer Controls. |
MIO_PIN_26 (IOU_SLCR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:8 | rwNormal read/write | 0x0 | reserved |
| L3_SEL | 7:5 | rwNormal read/write | 0x0 | Level 3 Mux Select: 0: GPIO [26] input/output bank 1. 1: CAN0 RX input. 2: I2C0 SCL input/output clock. 3: PJTAG TCK input clock. 4: SPI0 SCLK clock input/output. 5: TTC2 clock input. 6: UART0 RxD input. 7: TracePort DQ[4] output. |
| L2_SEL | 4:3 | rwNormal read/write | 0x0 | Level 2 Mux Select: 0: Level 3 Mux output 1: PMU GPI1 [10] input. 2: Scan Test [26] input/output. 3: CSU MIO External Tamper input. |
| L1_SEL | 2 | rwNormal read/write | 0x0 | Level 1 Mux Select: 0: Level 2 Mux output 1: NAND Chip Enable output. |
| L0_SEL | 1 | rwNormal read/write | 0x0 | Level 0 Mux Select: 0: Level 1 Mux output 1: GEM0 RGMII Tx Clock output. |
| Reserved | 0 | rwNormal read/write | 0x0 | reserved |