DTPR0 (DDR_PHY) Register Description
| Register Name | DTPR0 |
|---|---|
| Offset Address | 0x0000000110 |
| Absolute Address | 0x00FD080110 (DDR_PHY) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x105A2D08 |
| Description | DRAM Timing Parameters Register 0 |
DTPR0 (DDR_PHY) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:29 | roRead-only | 0x0 | Reserved. Return zeroes on reads. |
| tRRD | 28:24 | rwNormal read/write | 0x10 | Activate to activate command delay (different banks). Valid values are 1 to 31. For DDR4, use tRRD_L (RAS-to-RAS delay for same bank group). Larger values give more conservative command-to-command timings |
| Reserved | 23 | roRead-only | 0x0 | Reserved. Return zeroes on reads. |
| tRAS | 22:16 | rwNormal read/write | 0x5A | Activate to precharge command delay. Larger values give more conservative command-to-command timings |
| Reserved | 15 | roRead-only | 0x0 | Reserved. Return zeroes on reads. |
| tRP | 14:8 | rwNormal read/write | 0x2D | Precharge command period: The minimum time between a precharge command and any other command. In LPDDR3 mode set this parameter as per tRPab(slow) - max(27ns,3nCK). Also in LPDDR3 mode, PUB adds an offset of 8 to the register value, so valid range is 8 to 2424. For all other protocols, set to the min specified value of tRP Larger values give more conservative command-to-command timings |
| Reserved | 7:5 | roRead-only | 0x0 | Reserved. Return zeroes on reads. |
| tRTP | 4:0 | rwNormal read/write | 0x8 | Internal minimum read to precharge command delay (tRTP) for DDR3 and LPDDR3 modes. Valid values are 2 to 15. Larger values give more conservative command-to-command timings In DDR4/LPDDR4 mode, tRTP is decoded based on corresponding MR register fields; this field is unused (don't-care) DDR 4: uses MR0[13], MR0[11:9] instead LPDDR4: uses MR2[2:0] instead |