GQSPI_CFG (QSPI) Register Description
| Register Name | GQSPI_CFG |
|---|---|
| Offset Address | 0x0000000100 |
| Absolute Address | 0x00FF0F0100 (QSPI) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | GQSPI Configuration |
Note: Change register value only when controller is not communicating with the memory device. Software Driver name: XGQSPIPS_CR
GQSPI_CFG (QSPI) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| MODE_EN | 31:30 | rwNormal read/write | 0x0 | Flash memory interface mode control: 00: IO mode. 10: DMA mode. 01,11: reserved. Software Driver name: XGQSPIPS_IF_MODE |
| GEN_FIFO_START_MODE | 29 | rwNormal read/write | 0x0 | Start mode of Generic FIFO Software Driver name: XGQSPIPS_CR_GENFIFO_START_MODE 0: Auto Start Mode. 1: Manual Start Mode. |
| START_GEN_FIFO | 28 | woWrite-only | 0x0 | Trigger Generic FIFO Command Execution. Software Driver name: XGQSPIPS_CR_START_GEN 0:disable executing requests. 1: enable executing requests. |
| Reserved | 27 | razRead as zero | 0x0 | reserved |
| ENDIAN | 26 | rwNormal read/write | 0x0 | Endian format transmit data register writes (GQSPI_TXD) and receive data register reads (GQSPI_RXD): 0: little endian. 1: big endian. Software Driver name: XGQSPIPS_CR_ENDIAN |
| Reserved | 25:21 | razRead as zero | 0x0 | reserved |
| EN_POLL_TIMEOUT | 20 | rwNormal read/write | 0x0 | Poll Timeout Enable: Software Driver name: XGQSPIPS_CR_EN_POLL_TIMEOUT Interrupt enable? 0: disable. 1: enable. |
| WP_HOLD | 19 | rwNormal read/write | 0x0 | If set, Holdb and WPn pins are actively driven by the qspi controller in 1-bit and 2-bit modes. If not set, then external pull up is required on HOLDb and WPn pins. Note that this bit doesn't affect the quad(4-bit) mode as Controller always drives these pins in quad mode. It is highly recommended to set this bit always(irrespective of mode of operation) while using GQSPI |
| Reserved | 18:6 | razRead as zero | 0x0 | reserved |
| BAUD_RATE_DIV | 5:3 | rwNormal read/write | 0x0 | Clock Prescaler: Software Driver name: XGQSPIPS_CR_BAUDRATE 000: divide by 2. 001: divide by 4. 010: divide by 8. 011: divide by 16. 100: divide by 32. 101: divide by 64. 110: divide by 128. 111: divide by 256. Note: 000 is requried for loopback, [USE_LPBK]. |
| CLK_PH | 2 | rwNormal read/write | 0x0 | Clock phase Software Driver name: XGQSPIPS_CR_CPHA 1: the QSPI clock is inactive outside the word 0: the QSPI clock is active outside the word Note: For {CLK_PH, CLK_POL}, only 2b11 and 2b00 are supported. |
| CLK_POL | 1 | rwNormal read/write | 0x0 | Clock polarity outside QSPI word. Software Driver name: XGQSPIPS_CR_CPOL 0: QSPI clock is quiescent low. 1: QSPI clock is quiescent high. Note: For [CLK_PH, CLK_POL], only 2b11 and 2b00 are supported. |
| Reserved | 0 | razRead as zero | 0x0 | reserved |