enable_spi_enable_clr0 (PL390) Register Description
| Register Name | enable_spi_enable_clr0 |
|---|---|
| Offset Address | 0x0000000184 |
| Absolute Address | 0x00F9000184 (RCPU_GIC) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | Interrupt Clear-Enable Registers (ICDICER) |
enable_spi_enable_clr0 (PL390) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| _ | 31:0 | rwNormal read/write | 0x0 | Refer to the Arm Generic Interrupt Controller Architecture Specification 2.0 for a detailed register descriptions. |