PP0_TILEBUFFER_BITS (GPU) Register - UG1087

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

PP0_TILEBUFFER_BITS (GPU) Register Description

Register NamePP0_TILEBUFFER_BITS
Offset Address0x0000008058
Absolute Address 0x00FD4B8058 (GPU)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionTilebuffer configuration Register

PP0_TILEBUFFER_BITS (GPU) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
_31:16rwNormal read/write0x0Reserved, write as zero, read undefined.
TILEBUFFER_A_BITS15:12rwNormal read/write0x0Number of bits allocated to the alpha component in the tilebuffer
TILEBUFFER_B_BITS11:8rwNormal read/write0x0Number of bits allocated to the blue component in the tilebuffer
TILEBUFFER_G_BITS 7:4rwNormal read/write0x0Number of bits allocated to the green component in the tilebuffer
TILEBUFFER_R_BITS 3:0rwNormal read/write0x0Number of bits allocated to the red component in the tilebuffer