Field Name | Bits | Type | Reset Value | Description |
TXPMD_TM_45_31_8_rsvd | 31:8 | roRead-only | 0x0 | Value generated by PCW. |
ana_dp_byp0_7_6_rsvd | 7:6 | roRead-only | 0x0 | Value generated by PCW. |
dp_TM_TX_dp_enable_post2_path | 5 | rwNormal read/write | 0x0 | Value generated by PCW. |
dp_TM_TX_ovrd_dp_enable_post2_path | 4 | rwNormal read/write | 0x0 | Value generated by PCW. |
dp_TM_TX_dp_enable_post1_path | 3 | rwNormal read/write | 0x0 | Value generated by PCW. |
dp_TM_TX_ovrd_dp_enable_post1_path | 2 | rwNormal read/write | 0x0 | Value generated by PCW. |
dp_TM_TX_dp_enable_main_path | 1 | rwNormal read/write | 0x0 | Value generated by PCW. |
dp_TM_TX_ovrd_dp_enable_main_path | 0 | rwNormal read/write | 0x0 | Value generated by PCW. |