BANK3_STATUS (CRL_APB) Register - BANK3_STATUS (CRL_APB) Register - UG1087

Zynq UltraScale+ Devices Register Reference (UG1087)
Document ID
UG1087
Release Date
2025-06-20
Revision
1.11

BANK3_STATUS (CRL_APB) Register Description

Register NameBANK3_STATUS
Offset Address0x0000000288
Absolute Address 0x00FF5E0288 (CRL_APB)
Width10
TyperoRead-only
Reset Value0x00000000
DescriptionVoltage mode status for DIO bank 3

Voltage Status: 0 = 2.5/3.3v mode. 1 = 1.8v mode. Note: Each bit applies to a single I/O pin.

BANK3_STATUS (CRL_APB) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
vmode_1p8_3p3_n 0roRead-only0Bit[9]: TCK
Bit[8]: TDI
Bit[7]: TMS
Bit[6]: TDO
Bit[5]: SRST
Bit[4]: PROG
Bit[3]: INIT
Bit[2]: DONE
Bit[1]: ERROR_OUT
Bit[0]: ERROR_STS