MBISR_CNTRL (PMU_LOCAL) Register Description
| Register Name | MBISR_CNTRL |
|---|---|
| Offset Address | 0x0000000330 |
| Absolute Address | 0x00FFD60330 (PMU_LOCAL) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | Controls the MBISR engines in the FPD. |
MBISR_CNTRL (PMU_LOCAL) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:6 | roRead-only | 0x0 | reserved |
| FPD_Group | 5 | rwNormal read/write | 0x0 | Apply MBISR for the FP domain. This needs to be set before Enable bit is set to 1 to start the MBISR operation. |
| Reserved | 4:1 | roRead-only | 0x0 | reserved |
| Enable | 0 | rwNormal read/write | 0x0 | This bit is driven by PMU to trigger the repair operation and needs to be 0 and then set to 1 after the FPD_Group is set to 1 in order to initialize MBISR chain on the FPD. Typically, the BISR chain is reset when this input is low. |