L0_PLL_STATUS_READ_1 (SERDES) Register Description
| Register Name | L0_PLL_STATUS_READ_1 |
|---|---|
| Offset Address | 0x00000023E4 |
| Absolute Address | 0x00FD4023E4 (SERDES) |
| Width | 32 |
| Type | roRead-only |
| Reset Value | 0x00000001 |
| Description | Register value is generated by Vivado PCW. |
L0_PLL_STATUS_READ_1 (SERDES) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| PLL_STATUS_READ_1_31_8_rsvd | 31:8 | roRead-only | 0x0 | Value generated by PCW. |
| pll_status_read_1_rsvd | 7:6 | roRead-only | 0x0 | Value generated by PCW. |
| pll_start_loop_status_read | 5 | roRead-only | 0x0 | Value generated by PCW. |
| pll_lock_status_read | 4 | roRead-only | 0x0 | Value generated by PCW. |
| pll_coarse_done_status_read | 3 | roRead-only | 0x0 | Value generated by PCW. |
| pll_coarse_code_msb_status_read | 2:0 | roRead-only | 0x1 | Value generated by PCW. |