OCM_CE_CNTRL (PMU_LOCAL) Register - UG1087

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2025-06-20
Revision
1.11

OCM_CE_CNTRL (PMU_LOCAL) Register Description

Register NameOCM_CE_CNTRL
Offset Address0x00000000C8
Absolute Address 0x00FFD600C8 (PMU_LOCAL)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x0000000F
DescriptionOCM Memory Chip Enables. Reset only by POR.

Chip Enable control signals. 0: disable memory. 1: enable memory. All fields can be read or written only by the PMU processor. This register maintains its contents during a System Reset.

OCM_CE_CNTRL (PMU_LOCAL) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:4roRead-only0x0reserved
Bank3 3rwNormal read/write0x1OCM Bank 3
Bank2 2rwNormal read/write0x1OCM Bank 2
Bank1 1rwNormal read/write0x1OCM Bank 1
Bank0 0rwNormal read/write0x1OCM Bank 0