SMMU_SIDR1 (SMMU500) Register - UG1087

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID: UG1087
Release Date: 2024-03-13
Revision: 1.10

SMMU_SIDR1 (SMMU500) Register Description

Register Name	SMMU_SIDR1
Offset Address	0x0000000024
Absolute Address	0x00FD800024 (SMMU_GPV)
Width	32
Type	roRead-only
Reset Value	0x30000F10
Description	Provides SMMU capability information.

SMMU_SIDR1 (SMMU500) Register Bit-Field Summary

Field Name	Bits	Type	Reset Value	Description
PAGESIZE	31	roRead-only	0x0	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
NUMPAGENDXB	30:28	roRead-only	0x3	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
NUMS2CB	23:16	roRead-only	0x0	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
SMCD	15	roRead-only	0x0	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
SSDTP	12	roRead-only	0x0	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
NUMSSDNDXB	11:8	roRead-only	0xF	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
NUMCB	7:0	roRead-only	0x10	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details