GSBUSCFG1 (USB3_XHCI) Register Description
| Register Name | GSBUSCFG1 |
|---|---|
| Offset Address | 0x000000C104 |
| Absolute Address |
0x00FE20C104 (USB3_0_XHCI) 0x00FE30C104 (USB3_1_XHCI) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | Global SoC Bus Configuration Register 1 xHCI Register Power-On Value: The standard xHCI driver does not access this register. |
GSBUSCFG1 (USB3_XHCI) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:13 | roRead-only | 0x0 | Reserved |
| EN1KPAGE | 12 | rwNormal read/write | 0 | 1k Page Boundary Enable By default (this bit is disabled) the AXI breaks transfers at the 4k page boundary. When this bit is enabled, the AXI master (DMA data) breaks transfers at the 1k page boundary. |
| PipeTransLimit | 11:8 | rwNormal read/write | 0 | AXI Pipelined Transfers Burst Request Limit The field controls the number of outstanding pipelined transfer requests the AXI master pushes to the AXI slave. When the AXI master reaches this limit, it does not make any more requests on the AXI ARADDR and AWADDR buses until the associated data phases complete. This field is encoded as follows: - h0: 1 request - h1: 2 requests - h2: 3 requests - h3: 4 requests - .. - hF: 16 requests |
| Reserved | 7:0 | roRead-only | 0x0 | Reserved |