INT_MASK_1 (GPIO) Register Description
| Register Name | INT_MASK_1 |
|---|---|
| Offset Address | 0x000000024C |
| Absolute Address | 0x00FF0A024C (GPIO) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x03FFFFFF |
| Description | Interrupt Mask Status (GPIO Bank1, MIO) |
This register operates in exactly the same manner as INT_MASK_0, except that it reflects bank1, which corresponds to MIO[51:26].
INT_MASK_1 (GPIO) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:26 | razRead as zero | 0x0 | Not used, read back as zero |
| INT_MASK_1 | 25:0 | roRead-only | 0x3FFFFFF | Interrupt mask 0: interrupt source enabled 1: interrupt source masked Each bit reports the status for the corresponding pin within the 26-bit bank |