PP0_INT_MASK (GPU) Register

Zynq UltraScale+ Devices Register Reference (UG1087)
Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

PP0_INT_MASK (GPU) Register Description

Register NamePP0_INT_MASK
Offset Address0x0000009028
Absolute Address 0x00FD4B9028 (GPU)
Width32
TyperwNormal read/write
Reset Value0x00000FFF
DescriptionInterrupt Mask Register

PP0_INT_MASK (GPU) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:13rwNormal read/write0x0Reserved, write as zero, read undefined.
RESET_COMPLETED12rwNormal read/write0x0Enables an interrupt if set to one
CALL_STACK_OVERFLOW11rwNormal read/write0x1Enables an interrupt if set to one
CALL_STACK_UNDERFLOW10rwNormal read/write0x1Enables an interrupt if set to one
INVALID_PLIST_COMMAND 9rwNormal read/write0x1Enables an interrupt if set to one
WRITE_BOUNDARY_ERROR 8rwNormal read/write0x1Enables an interrupt if set to one
CNT_1_LIMIT 7rwNormal read/write0x1Enables an interrupt if set to one
CNT_0_LIMIT 6rwNormal read/write0x1Enables an interrupt if set to one
BUS_STOP 5rwNormal read/write0x1Enables an interrupt if set to one
BUS_ERROR 4rwNormal read/write0x1Enables an interrupt if set to one
FORCE_HANG 3rwNormal read/write0x1Enables an interrupt if set to one
HANG 2rwNormal read/write0x1Enables an interrupt if set to one
END_OF_TILE 1rwNormal read/write0x1Enables an interrupt if set to one
END_OF_FRAME 0rwNormal read/write0x1Enables an interrupt if set to one