SD_DDR50PRESET (IOU_SLCR) Register - UG1087

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2025-06-20
Revision
1.11

SD_DDR50PRESET (IOU_SLCR) Register Description

Register NameSD_DDR50PRESET
Offset Address0x0000000344
Absolute Address 0x00FF180344 (IOU_SLCR)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00020002
DescriptionPreset Value for DDR50

SD_DDR50PRESET (IOU_SLCR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:29razRead as zero0x0Reserved. Writes are ignored, read data is zero.
SD1_DDR50PRESET28:16rwNormal read/write0x2SD1 Preset Value for DDR50
Reserved15:13razRead as zero0x0Reserved. Writes are ignored, read data is zero.
SD0_DDR50PRESET12:0rwNormal read/write0x2SD0 Preset Value for DDR50