MIO_PIN_59 (IOU_SLCR) Register - UG1087

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2025-06-20
Revision
1.11

MIO_PIN_59 (IOU_SLCR) Register Description

Register NameMIO_PIN_59
Offset Address0x00000000EC
Absolute Address 0x00FF1800EC (IOU_SLCR)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionMIO Device Pin 59 Multiplexer Controls.

MIO_PIN_59 (IOU_SLCR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:8rwNormal read/write0x0reserved
L3_SEL 7:5rwNormal read/write0x0Level 3 Mux Select:
0: GPIO [59] input/output bank 2.
1: CAN0 TX output.
2: I2C0 SDA input/output.
3: PJTAG TDI input.
4: SPI1 SS [2] output.
5: TTC2 waveform output.
6: UART0 TxD output.
7: TracePort DQ[5] output.
L2_SEL 4:3rwNormal read/write0x0Level 2 Mux Select:
0: Level 3 Mux output
1: reserved
2: reserved
3: reserved
L1_SEL 2rwNormal read/write0x0Level 1 Mux Select:
0: Level 2 Mux output
1: USB0 ULPI Data [3] input/output.
L0_SEL 1rwNormal read/write0x0Level 0 Mux Select:
0: Level 1 Mux output
1: GEM2 RGMII Rx Data [0] input.
Reserved 0rwNormal read/write0x0reserved