RPU_INTR_MASK_0 (RPU) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

RPU_INTR_MASK_0 (RPU) Register Description

Register NameRPU_INTR_MASK_0
Offset Address0x0000000040
Absolute Address 0x00FF9A0040 (RPU)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionRPU Interrupt Injection Mask register

RPU_INTR_MASK_0 (RPU) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
SPI31:0rwNormal read/write0x0Software use these to inject interrupt for GIC safety check
0 = interrupt is disabled
1 = if bit in correcdonding register is set, interrupt is enabled to GIC