MIO_PIN_74 (IOU_SLCR) Register - UG1087

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

MIO_PIN_74 (IOU_SLCR) Register Description

Register NameMIO_PIN_74
Offset Address0x0000000128
Absolute Address 0x00FF180128 (IOU_SLCR)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionMIO Device Pin 74 Multiplexer Controls.

MIO_PIN_74 (IOU_SLCR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:8rwNormal read/write0x0reserved
L3_SEL 7:5rwNormal read/write0x0Level 3 Mux Select:
0: GPIO [74] input/output bank 2.
1: CAN0 RX input.
2: I2C0 SCL input/output clock.
3: LPD SWDT clock output.
4: SPI1 MISO input/output.
5: reserved
6: UART0 RxD input.
7: reserved
L2_SEL 4:3rwNormal read/write0x0Level 2 Mux Select:
0: Level 3 Mux output
1: SDIO0 Data [7] input/output.
2: SDIO1 Data [3] input/output.
3: reserved
L1_SEL 2rwNormal read/write0x0Level 1 Mux Select:
0: Level 2 Mux output
1: USB1 ULPI Data [6] input/output.
L0_SEL 1rwNormal read/write0x0Level 0 Mux Select:
0: Level 1 Mux output
1: GEM3 RGMII Rx Data [3] input.
Reserved 0rwNormal read/write0x0reserved