GICP_PMU_IRQ_MASK (LPD_SLCR) Register Description
| Register Name | GICP_PMU_IRQ_MASK |
|---|---|
| Offset Address | 0x00000080A4 |
| Absolute Address | 0x00FF4180A4 (LPD_SLCR) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x0000001F |
| Description | Interrupt Mask Register for intrN. This is a read-only location and can be atomically altered by either the IDR or the IER. |
GICP_PMU_IRQ_MASK (LPD_SLCR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:8 | razRead as zero | 0x0 | Reserved for future use |
| src4 | 4 | roRead-only | 0x1 | Create single interrupt source for PMU from GICP4 |
| src3 | 3 | roRead-only | 0x1 | Create single interrupt source for PMU from GICP3 |
| src2 | 2 | roRead-only | 0x1 | Create single interrupt source for PMU from GICP2 |
| src1 | 1 | roRead-only | 0x1 | Create single interrupt source for PMU from GICP1 |
| src0 | 0 | roRead-only | 0x1 | Create single interrupt source for PMU from GICP0 |