GICP0_IRQ_STATUS (LPD_SLCR) Register - GICP0_IRQ_STATUS (LPD_SLCR) Register - UG1087

Zynq UltraScale+ Devices Register Reference (UG1087)
Document ID
UG1087
Release Date
2025-06-20
Revision
1.11

GICP0_IRQ_STATUS (LPD_SLCR) Register Description

Register NameGICP0_IRQ_STATUS
Offset Address0x0000008000
Absolute Address 0x00FF418000 (LPD_SLCR)
Width32
TypewtcReadable, write a 1 to clear
Reset Value0x00000000
DescriptionGIC Proxy Interrupt Status (1/2)

Register for intrN. This is a sticky register that holds the value of the interrupt until cleared by a value of 1.

GICP0_IRQ_STATUS (LPD_SLCR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
src3131wtcReadable, write a 1 to clear0x0PL_IPI2: OR of all of IPIs targeted to RPU PL2
src3030wtcReadable, write a 1 to clear0x0PL_IPI1: OR of all of IPIs targeted to RPU PL1
src2929wtcReadable, write a 1 to clear0x0PL_IPI0: OR of all of IPIs targeted to RPU PL0
src2828wtcReadable, write a 1 to clear0x0Clock monitor coming from CRL
src2727wtcReadable, write a 1 to clear0x0RTC Seconds Interrupt
src2626wtcReadable, write a 1 to clear0x0RTC Alarm Interupt
src2525wtcReadable, write a 1 to clear0x0APM_LPD: Ord of all LPD APMs
src2424wtcReadable, write a 1 to clear0x0CAN1 interrupt
src2323wtcReadable, write a 1 to clear0x0CAN0 interrupt
src2222wtcReadable, write a 1 to clear0x0UART1 interrupt
src2121wtcReadable, write a 1 to clear0x0UART0 interrupt
src2020wtcReadable, write a 1 to clear0x0SPI1 interrupt
src1919wtcReadable, write a 1 to clear0x0SPI0 interrupt
src1818wtcReadable, write a 1 to clear0x0I2C1 interrupt
src1717wtcReadable, write a 1 to clear0x0I2C0 interrupt
src1616wtcReadable, write a 1 to clear0x0GPIO interrupt
src1515wtcReadable, write a 1 to clear0x0SPI interrupt
src1414wtcReadable, write a 1 to clear0x0NAND/NOR/SRAM Static Memory Controller Interrupt
src1313wtcReadable, write a 1 to clear0x0RPU CPU1 ECC errors interrupt. All ECC interrupt of CPU1 are combined into this interrup
src1212wtcReadable, write a 1 to clear0x0RPU CPU0 ECC errors interrupt. All ECC interrupt of CPU0 are combined into this interrupt
src1111wtcReadable, write a 1 to clear0x0LPD_APB_INT: ORd of all APB interrupts from LPD
src1010wtcReadable, write a 1 to clear0x0OCM interrupt (error)
src9 9wtcReadable, write a 1 to clear0x0RPU performance monitor
src8 8wtcReadable, write a 1 to clear0x0RPU performance monitor