QSPI_DATA_DLY_ADJ (QSPI) Register Description
| Register Name | QSPI_DATA_DLY_ADJ |
|---|---|
| Offset Address | 0x00000001F8 |
| Absolute Address | 0x00FF0F01F8 (QSPI) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | QSPI RX Data Delay |
QSPI RX Data Delay Register Register for adjusting the internal receive data delay for read data capturing. This feature is only active when [USE_LPBK] is active and Flash clock is around 100MHz Software Driver name: XGQSPIPS_ECO
QSPI_DATA_DLY_ADJ (QSPI) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| USE_DATA_DLY | 31 | rwNormal read/write | 0x0 | Enable using delay elements in receive data path Software Driver name: XGQSPIPS_POLL_UPPER 0: Disable data delay 1: Enable data delay Note: Change this value only when controller is not communicating with the memory device. |
| DATA_DLY_ADJ | 30:28 | rwNormal read/write | 0x0 | Delay adjustment value Software Driver name: XGQSPIPS_LPBK_DLY1 Note: Change this value only when controller is not communicating with the memory device. |
| Reserved | 27:0 | rwNormal read/write | 0x0 | reserved |