screening_type_1_register_1 (GEM) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

screening_type_1_register_1 (GEM) Register Description

Register Namescreening_type_1_register_1
Offset Address0x0000000504
Absolute Address 0x00FF0B0504 (GEM0)
0x00FF0C0504 (GEM1)
0x00FF0D0504 (GEM2)
0x00FF0E0504 (GEM3)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionScreening type 1 registers are used to allocate two priority queues to received frames based on certain IP or UDP fields of incoming frames. Firstly, when DS/TC match enable is set (bit 28), the DS (Differentiated Services) field of the received IPv4 header or TCfield (traffic class) of IPv6 headers are matched against bits 11:4. Secondly, when UDP port match enable is set (bit 29), the UDP Destination Port of the received UDP frame is matched against bits 27:12. Both UDP and DS/TC matching can be enabled simultaneously or individually. If a match is successful, then the queue value programmed in bits 3:0 is allocated to the frame. The required number of Type 1 screening registers is configured in the gem defines file. Up to 16 type 1 screening registers have been allocated APB address space between 0x500 and 0x53C.

screening_type_1_register_1 (GEM) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:30roRead-only0x0Reserved, read as 0, ignored on write.
udp_port_match_enable29rwNormal read/write0x0UDP port match enable
dstc_enable28rwNormal read/write0x0DS/TC Enable
udp_port_match27:12rwNormal read/write0x0UDP Port Match
dstc_match11:4rwNormal read/write0x0DS/TC Match
queue_number 3:0rwNormal read/write0x0Queue Number (0-> 1)