CPU_R5_CTRL (CRL_APB) Register Description
| Register Name | CPU_R5_CTRL |
|---|---|
| Offset Address | 0x0000000090 |
| Absolute Address | 0x00FF5E0090 (CRL_APB) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x03000600 |
| Description | RPU MPCore and OCM Clock Generator Config |
CPU_R5_CTRL (CRL_APB) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:26 | rwNormal read/write | 0x0 | reserved |
| CLKACT_CORE | 25 | rwNormal read/write | 0x1 | Clock active control. 0: disable. 1: enable. |
| CLKACT | 24 | rwNormal read/write | 0x1 | Turing this off will shut down the OCM, some parts of the APM, and prevent transactions going from the FPD to the LPD and could lead to system hang |
| Reserved | 23:14 | rwNormal read/write | 0x0 | reserved |
| DIVISOR0 | 13:8 | rwNormal read/write | 0x6 | 6-bit divider. |
| Reserved | 7:3 | rwNormal read/write | 0x0 | reserved |
| SRCSEL | 2:0 | rwNormal read/write | 0x0 | Clock generator input source. 000: RPLL 010: IOPLL 011: DPLL_CLK_TO_LPD |