GP_CONTR_REG_PLB_ALLOC_START_ADDR (GPU) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

GP_CONTR_REG_PLB_ALLOC_START_ADDR (GPU) Register Description

Register NameGP_CONTR_REG_PLB_ALLOC_START_ADDR
Offset Address0x0000000010
Absolute Address 0x00FD4B0010 (GPU)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionGP Control Register PLB Allocate Start Address

GP_CONTR_REG_PLB_ALLOC_START_ADDR (GPU) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
GP_CONTR_REG_PLB_ALLOC_START_ADDR31:7rwNormal read/write0x0Start/current address for the polygon list allocation
Reserved 6:0rwNormal read/write0x0Reserved, write as zero, read undefined