IMR_0 (SMMU_REG) Register - UG1087

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID: UG1087
Release Date: 2024-03-13
Revision: 1.10

IMR_0 (SMMU_REG) Register Description

Register Name	IMR_0
Offset Address	0x0000000014
Absolute Address	0x00FD5F0014 (SMMU_REG)
Width	32
Type	mixedMixed types. See bit-field details.
Reset Value	0x8000001F
Description	Interrupt Mask Register. This is a read-only location and can be atomically altered by either the IDR or the IER.

IMR_0 (SMMU_REG) Register Bit-Field Summary

Field Name	Bits	Type	Reset Value	Description
addr_decode_err	31	wtcReadable, write a 1 to clear	0x1	Address Decode Error
Reserved	30:5	roRead-only	0x0	Reserved
gbl_flt_irpt_ns	4	roRead-only	0x1	Interrupt Mask value for gbl_flt_irpt_ns interrupt.
gbl_flt_irpt_s	3	roRead-only	0x1	Interrupt Mask value for gbl_flt_irpt_s interrupt.
comb_perf_irpt_TBU	2	roRead-only	0x1	Interrupt Mask value for comb_perf_irpt_TBU interrupt.
comb_irpt_s	1	roRead-only	0x1	Interrupt Mask value for comb_irpt_s interrupt.
comb_irpt_ns	0	roRead-only	0x1	Interrupt Mask value for comb_irpt_ns interrupt.