DP_STC_REF_CTRL (CRF_APB) Register Description
| Register Name | DP_STC_REF_CTRL |
|---|---|
| Offset Address | 0x000000007C |
| Absolute Address | 0x00FD1A007C (CRF_APB) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x01203200 |
| Description | DisplayPort System Time Clock Generator Control. |
DP_STC_REF_CTRL (CRF_APB) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| CLKACT | 24 | rwNormal read/write | 0x1 | Clock active control. 0: disable. Clock stop. 1: enable. |
| DIVISOR1 | 21:16 | rwNormal read/write | 0x20 | 6-bit divider. |
| DIVISOR0 | 13:8 | rwNormal read/write | 0x32 | 6-bit divider. |
| SRCSEL | 2:0 | rwNormal read/write | 0x0 | Clock generator input source. 000: VPLL 010: DPLL 011: RPLL_TO_FPD |