DBGCMD (DDRC) Register Description
| Register Name | DBGCMD |
|---|---|
| Offset Address | 0x000000030C |
| Absolute Address | 0x00FD07030C (DDRC) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | Command Debug Register |
This register is dynamic. Dynamic registers can be written at any time during operation.
DBGCMD (DDRC) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| hw_ref_zq_en | 31 | rwNormal read/write | 0x0 | Setting this register bit to 1 allows refresh and ZQCS commands to be triggered from hardware via the IOs ext_*. If set to 1, the fields DBGCMD.zq_calib_short and DBGCMD.rank*_refresh have no function, and are ignored by the DDRC logic. Setting this register bit to 0 allows refresh and ZQCS to be triggered from software, via the fields DBGCMD.zq_calib_short and DBGCMD.rank*_refresh. If set to 0, the hardware pins ext_* have no function, and are ignored by the DDRC logic. This register is static, and may only be changed when the DDRC reset signal, core_ddrc_rstn, is asserted (0). |
| ctrlupd | 5 | rwNormal read/write | 0x0 | Setting this register bit to 1 indicates to the DDRC to issue a dfi_ctrlupd_req to the PHY. When this request is stored in the DDRC, the bit is automatically cleared. This operation must only be performed when DFIUPD0.dis_auto_ctrlupd=1. |
| zq_calib_short | 4 | rwNormal read/write | 0x0 | Setting this register bit to 1 indicates to the DDRC to issue a ZQCS (ZQ calibration short)/MPC(ZQ calibration) command to the SDRAM. When this request is stored in the DDRC, the bit is automatically cleared. This operation can be performed only when ZQCTL0.dis_auto_zq=1. It is recommended NOT to set this register bit if in Init operating mode. This register bit is ignored when in Self-Refresh(except LPDDR4) and SR-Powerdown(LPDDR4) and Deep power-down operating modes and Maximum Power Saving Mode. |
| rank1_refresh | 1 | rwNormal read/write | 0x0 | Setting this register bit to 1 indicates to the DDRC to issue a refresh to rank 1. Writing to this bit causes DBGSTAT.rank1_refresh_busy to be set. When DBGSTAT.rank1_refresh_busy is cleared, the command has been stored in DDRC. This operation can be performed only when RFSHCTL3.dis_auto_refresh=1. It is recommended NOT to set this register bit if in Init or Deep power-down operating modes or Maximum Power Saving Mode. |
| rank0_refresh | 0 | rwNormal read/write | 0x0 | Setting this register bit to 1 indicates to the DDRC to issue a refresh to rank 0. Writing to this bit causes DBGSTAT.rank0_refresh_busy to be set. When DBGSTAT.rank0_refresh_busy is cleared, the command has been stored in DDRC. This operation can be performed only when RFSHCTL3.dis_auto_refresh=1. It is recommended NOT to set this register bit if in Init or Deep power-down operating modes or Maximum Power Saving Mode. |