OVSCLR_EL0 (A53_PMU_1) Register Description
| Register Name | OVSCLR_EL0 |
|---|---|
| Offset Address | 0x0000000C80 |
| Absolute Address | 0x00FED30C80 (CORESIGHT_A53_PMU_1) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | Performance Monitors Overflow Flag Status Clear Register |
OVSCLR_EL0 (A53_PMU_1) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| C | 31 | rwNormal read/write | 0x0 | PMCCNTR_EL0 overflow bit. Possible values are:PMCR_EL0.LC is used to control from which bit of PMCCNTR_EL0 (bit 31 or bit 63) an overflow is detected. |
| P | 30:0 | rwNormal read/write | 0x0 | Event counter overflow clear bit for EVCNTR<x>.N is the value in PMCR_EL0.N. Bits [30:N] are RAZ/WI.Possible values of each bit are: |