OEN_0 (GPIO) Register Description
| Register Name | OEN_0 |
|---|---|
| Offset Address | 0x0000000208 |
| Absolute Address | 0x00FF0A0208 (GPIO) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | Output enable (GPIO Bank0, MIO) |
When the IO is configured as an output, this controls whether the output is enabled or not. When the output is disabled, the pin is tri-stated. NOTE: The MIO driver setting MIO_MST_TRIx (IOU_SLCR) must be disabled (i.e. set to 0) for this field to be operational. When the MIO tri-state is enabled, the driver is disabled regardless of this GPIO setting. This register controls bank0, which corresponds to MIO[25:0].
OEN_0 (GPIO) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:26 | razRead as zero | 0x0 | Not used, read back as zero |
| OP_ENABLE_0 | 25:0 | rwNormal read/write | 0x0 | Output enables 0: disabled 1: enabled Each bit configures the corresponding pin within the 26-bit bank |