ATTR_36 (PCIE_ATTRIB) Register Description
| Register Name | ATTR_36 |
|---|---|
| Offset Address | 0x0000000090 |
| Absolute Address | 0x00FD480090 (PCIE_ATTRIB) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00007FFF |
| Description | ATTR_36 |
This register should only be written to during reset of the PCIe block
ATTR_36 (PCIE_ATTRIB) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| attr_link_cap_l1_exit_latency_comclk_gen1 | 14:12 | rwNormal read/write | 0x7 | Sets the exit latency from L1 state to be applied (at 2.5G) where a common clock is used. Transferred to the Link Capabilities register. |
| attr_link_cap_l0s_exit_latency_gen2 | 11:9 | rwNormal read/write | 0x7 | Sets the exit latency from L0s state to be applied (at 5G) where separate clocks are used. Transferred to the Link Capabilities register. |
| attr_link_cap_l0s_exit_latency_gen1 | 8:6 | rwNormal read/write | 0x7 | Sets the exit latency from L0s state to be applied (at 2.5G) where separate clocks are used. Transferred to the Link Capabilities register. |
| attr_link_cap_l0s_exit_latency_comclk_gen2 | 5:3 | rwNormal read/write | 0x7 | Sets the exit latency from L0s state to be applied (at 5G) where a common clock is used. Transferred to the Link Capabilities register. |
| attr_link_cap_l0s_exit_latency_comclk_gen1 | 2:0 | rwNormal read/write | 0x7 | Sets the exit latency from L0s state to be applied (at 2.5G) where a common clock is used. Transferred to the Link Capabilities register. |