SEQ_LOW_RATE_CHANNEL2 (PLSYSMON) Register - SEQ_LOW_RATE_CHANNEL2 (PLSYSMON) Register - UG1087

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2025-06-20
Revision
1.11

SEQ_LOW_RATE_CHANNEL2 (PLSYSMON) Register Description

Register NameSEQ_LOW_RATE_CHANNEL2
Offset Address0x00000001F0
Absolute Address 0x00FFA50DF0 (AMS_PL_SYSMON)
Width16
TyperwNormal read/write
Reset Value0x00000000
DescriptionLow-Rate Sequence Channel, Group 2.

SEQ_LOW_RATE_CHANNEL2 (PLSYSMON) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
channel215:0rwNormal read/write0x0Refer to SEQ_CHANNEL2 register for bit assignments.