ERROR_EN_2 (PMU_GLOBAL) Register Description
| Register Name | ERROR_EN_2 |
|---|
| Offset Address | 0x00000005A4 |
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| Absolute Address |
0x00FFD805A4 (PMU_GLOBAL)
|
|---|
| Width | 32 |
|---|
| Type | rwNormal read/write |
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| Reset Value | 0x073E0000 |
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| Description | System Error Enables, Reg 2. |
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Individual errors can be: 0: blocked. 1: propagated. The ERROR_EN_{1, 2} registers block errors generated in the system from reaching the error interrupt logic: ERR_INT*, ERR_POR*, ERR_SRST* and ERR_SIG*. If an error is blocked, it is blocked before the ERROR_STATUS_{1, 2} read registers. For details on the bit fields, refer to the ERROR_STATUS_2 register description.
ERROR_EN_2 (PMU_GLOBAL) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|
| Reserved | 31:27 | rwNormal read/write | 0x0 | reserved |
| CSU_ROM | 26 | rwNormal read/write | 0x1 | CSU BootROM Sequence failure. |
| PMU_PB | 25 | rwNormal read/write | 0x1 | PMU Pre-BootROM Sequence failure. |
| PMU_SERVICE | 24 | rwNormal read/write | 0x1 | Service Request error. |
| Reserved | 23:22 | rwNormal read/write | 0x0 | reserved |
| PMU_FW | 21:18 | rwNormal read/write | 0xF | Four (4) Firmware defined interrupt bits. |
| PMU_UC | 17 | rwNormal read/write | 0x1 | PMU Hardware failure or access error. |
| CSU | 16 | rwNormal read/write | 0x0 | CSU Hardware failure. |
| Reserved | 15:13 | rwNormal read/write | 0x0 | reserved |
| PLL_LOCK | 12:8 | rwNormal read/write | 0x0 | PLL Clock Locking errors. |
| Reserved | 7:6 | rwNormal read/write | 0x0 | reserved |
| PL | 5:2 | rwNormal read/write | 0x0 | Four (4) Error Signals from the PL. |
| TO | 1:0 | rwNormal read/write | 0x0 | ATB Timeouts for LPD and FPD. |