isr (FPD_SLCR_SECURE) Register - UG1087

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

isr (FPD_SLCR_SECURE) Register Description

Register Nameisr
Offset Address0x0000000008
Absolute Address 0x00FD690008 (FPD_SLCR_SECURE)
Width 1
TypewtcReadable, write a 1 to clear
Reset Value0x00000000
DescriptionInterrupt Status and clear.

Sticky register that holds the value of the interrupt until cleared by writing a value of 1.

isr (FPD_SLCR_SECURE) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
addr_decode_err 0wtcReadable, write a 1 to clear0x0Status for an address decode error.
Reads:
0: No Event.
1: Event Occurred.
Writes:
0: ignored.
1: clear bit.