ERROR_SRST_MASK_2 (PMU_GLOBAL) Register Description
| Register Name | ERROR_SRST_MASK_2 |
|---|---|
| Offset Address | 0x0000000574 |
| Absolute Address | 0x00FFD80574 (PMU_GLOBAL) |
| Width | 32 |
| Type | roRead-only |
| Reset Value | 0x073F1F3F |
| Description | System Errors to Reset; Interrupt Mask, Reg 2. |
0: unmasked (enabled). 1: masked (disabled). If the status bit = 1 (asserted interrupt) and the mask bit = 0 (not masked), then the IRQ to the interrupt controllers is asserted. Software checks the ISR to determine the cause of the interrupt. Read-only. For details on the bit fields, refer to the ERROR_STATUS_2 register description. The [PMU_PB] and [CSU_ROM] bits are reset only by the PS_POR_B signal (external).
ERROR_SRST_MASK_2 (PMU_GLOBAL) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:27 | roRead-only | 0x0 | reserved |
| CSU_ROM | 26 | roRead-only | 0x1 | CSU BootROM Sequence failure. Bit is reset only by the PS_POR_B reset signal pin. |
| PMU_PB | 25 | roRead-only | 0x1 | PMU Pre-BootROM Sequence failure. Bit is reset only by the PS_POR_B reset signal pin. |
| PMU_SERVICE | 24 | roRead-only | 0x1 | Service Request error. |
| Reserved | 23:22 | roRead-only | 0x0 | reserved |
| PMU_FW | 21:18 | roRead-only | 0xF | Four (4) Firmware defined interrupt bits. |
| PMU_UC | 17 | roRead-only | 0x1 | PMU Hardware failure or access error. |
| CSU | 16 | roRead-only | 0x1 | CSU Hardware failure. |
| Reserved | 15:13 | roRead-only | 0x0 | reserved |
| PLL_LOCK | 12:8 | roRead-only | 0x1F | PLL Clock Locking errors. |
| Reserved | 7:6 | roRead-only | 0x0 | reserved |
| PL | 5:2 | roRead-only | 0xF | Four (4) Error Signals from the PL. |
| TO | 1:0 | roRead-only | 0x3 | ATB Timeouts for LPD and FPD. |