IPI Module - UG1087

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID

UG1087

Release Date

2025-06-20

Revision

1.11

IPI Module Description

Module Type	IPI Module
Modules of this Type	IPI
Base Addresses	0x00FF300000 (IPI)
Description	Inter Processor Interrupts

IPI Module Register Summary

Register Name	Offset Address	Width	Type	Reset Value	Description
APU_TRIG	0x0000000000	32	mixedMixed types. See bit-field details.	0x00000000	Ch 0 Interrupt Trigger (sender). Default APU MPCore.
APU_OBS	0x0000000004	32	roRead-only	0x00000000	Ch 0 Interrupt Observation (sender).
APU_ISR	0x0000000010	32	mixedMixed types. See bit-field details.	0x00000000	Ch 0 Interrupt Status and Clear (receiver). Default APU MPCore.
APU_IMR	0x0000000014	32	roRead-only	0x0F0F0301	Ch 0 Interrupt Mask (receiver).
APU_IER	0x0000000018	32	mixedMixed types. See bit-field details.	0x00000000	Ch 0 Interrupt Enable (receiver).
APU_IDR	0x000000001C	32	mixedMixed types. See bit-field details.	0x00000000	Ch 0 Interrupt Disable (receiver).
RPU_0_TRIG	0x0000010000	32	mixedMixed types. See bit-field details.	0x00000000	Ch 1 Interrupt Trigger (sender). Default RPU0.
RPU_0_OBS	0x0000010004	32	roRead-only	0x00000000	Ch 1 Interrupt Observation (sender).
RPU_0_ISR	0x0000010010	32	mixedMixed types. See bit-field details.	0x00000000	Ch 1 Interrupt Status and Clear (receiver). Default RPU0.
RPU_0_IMR	0x0000010014	32	roRead-only	0x0F0F0301	Ch 1 Interrupt Mask (receiver).
RPU_0_IER	0x0000010018	32	mixedMixed types. See bit-field details.	0x00000000	Ch 1 Interrupt Enable (receiver).
RPU_0_IDR	0x000001001C	32	mixedMixed types. See bit-field details.	0x00000000	Ch 1 Interrupt Disable (receiver).
RPU_1_TRIG	0x0000020000	32	mixedMixed types. See bit-field details.	0x00000000	Ch 2 Interrupt Trigger (sender). Default RPU1.
RPU_1_OBS	0x0000020004	32	roRead-only	0x00000000	Ch 2 Interrupt Observation (sender).
RPU_1_ISR	0x0000020010	32	mixedMixed types. See bit-field details.	0x00000000	Ch 2 Interrupt Status and Clear (receiver). Default RPU1.
RPU_1_IMR	0x0000020014	32	roRead-only	0x0F0F0301	Ch 2 Interrupt Mask (receiver).
RPU_1_IER	0x0000020018	32	mixedMixed types. See bit-field details.	0x00000000	Ch 2 Interrupt Enable (receiver).
RPU_1_IDR	0x000002001C	32	mixedMixed types. See bit-field details.	0x00000000	Ch 1 Interrupt Disable (receiver).
PMU_0_TRIG	0x0000030000	32	mixedMixed types. See bit-field details.	0x00000000	PMU 0 Interrupt Trigger (sender).
PMU_0_OBS	0x0000030004	32	roRead-only	0x00000000	PMU 0 Interrupt Observation (sender).
PMU_0_ISR	0x0000030010	32	mixedMixed types. See bit-field details.	0x00000000	PMU 0 Interrupt Status and Clear (receiver).
PMU_0_IMR	0x0000030014	32	roRead-only	0x0F0F0301	PMU 0 Interrupt Mask (receiver).
PMU_0_IER	0x0000030018	32	mixedMixed types. See bit-field details.	0x00000000	PMU 0 Interrupt Enable (receiver).
PMU_0_IDR	0x000003001C	32	mixedMixed types. See bit-field details.	0x00000000	PMU 0 Interrupt Disable (receiver).
PMU_1_TRIG	0x0000031000	32	mixedMixed types. See bit-field details.	0x00000000	PMU 1 Interrupt Trigger (sender).
PMU_1_OBS	0x0000031004	32	roRead-only	0x00000000	PMU 1 Interrupt Observation (sender).
PMU_1_ISR	0x0000031010	32	mixedMixed types. See bit-field details.	0x00000000	PMU 1 Interrupt Status and Clear (receiver).
PMU_1_IMR	0x0000031014	32	roRead-only	0x0F0F0301	PMU 1 Interrupt Mask (receiver).
PMU_1_IER	0x0000031018	32	mixedMixed types. See bit-field details.	0x00000000	PMU 1 Interrupt Enable (receiver).
PMU_1_IDR	0x000003101C	32	mixedMixed types. See bit-field details.	0x00000000	PMU 1 Interrupt Disable (receiver).
PMU_2_TRIG	0x0000032000	32	mixedMixed types. See bit-field details.	0x00000000	PMU 2 Interrupt Trigger (sender).
PMU_2_OBS	0x0000032004	32	roRead-only	0x00000000	PMU 2 Interrupt Observation (sender).
PMU_2_ISR	0x0000032010	32	mixedMixed types. See bit-field details.	0x00000000	PMU 2 Interrupt Status and Clear (receiver).
PMU_2_IMR	0x0000032014	32	roRead-only	0x0F0F0301	PMU 2 Interrupt Mask (receiver).
PMU_2_IER	0x0000032018	32	mixedMixed types. See bit-field details.	0x00000000	PMU 2 Interrupt Enable (receiver).
PMU_2_IDR	0x000003201C	32	mixedMixed types. See bit-field details.	0x00000000	PMU 2 Interrupt Disable (receiver).
PMU_3_TRIG	0x0000033000	32	mixedMixed types. See bit-field details.	0x00000000	PMU 3 Interrupt Trigger (sender).
PMU_3_OBS	0x0000033004	32	roRead-only	0x00000000	PMU 3 Interrupt Observation (sender).
PMU_3_ISR	0x0000033010	32	mixedMixed types. See bit-field details.	0x00000000	PMU 3 Interrupt Status and Clear (receiver).
PMU_3_IMR	0x0000033014	32	roRead-only	0x0F0F0301	PMU 3 Interrupt Mask (receiver).
PMU_3_IER	0x0000033018	32	mixedMixed types. See bit-field details.	0x00000000	PMU 3 Interrupt Enable (receiver).
PMU_3_IDR	0x000003301C	32	mixedMixed types. See bit-field details.	0x00000000	PMU 3 Interrupt Disable (receiver).
PL_0_TRIG	0x0000040000	32	mixedMixed types. See bit-field details.	0x00000000	Ch 7 Interrupt Trigger (sender). Default PL 0.
PL_0_OBS	0x0000040004	32	roRead-only	0x00000000	Ch 7 Interrupt Observation (sender).
PL_0_ISR	0x0000040010	32	mixedMixed types. See bit-field details.	0x00000000	Ch 7 Interrupt Status and Clear (receiver). Default PL 0.
PL_0_IMR	0x0000040014	32	roRead-only	0x0F0F0301	Ch 7 Interrupt Mask (receiver).
PL_0_IER	0x0000040018	32	mixedMixed types. See bit-field details.	0x00000000	Ch 7 Interrupt Enable (receiver).
PL_0_IDR	0x000004001C	32	mixedMixed types. See bit-field details.	0x00000000	Ch 7 Interrupt Disable (receiver).
PL_1_TRIG	0x0000050000	32	mixedMixed types. See bit-field details.	0x00000000	Ch 8 Interrupt Trigger (sender). Default PL 1.
PL_1_OBS	0x0000050004	32	roRead-only	0x00000000	Ch 8 Interrupt Observation (sender).
PL_1_ISR	0x0000050010	32	mixedMixed types. See bit-field details.	0x00000000	Ch 8 Interrupt Status and Clear (receiver). Default PL 1.
PL_1_IMR	0x0000050014	32	roRead-only	0x0F0F0301	Ch 8 Interrupt Mask (receiver).
PL_1_IER	0x0000050018	32	mixedMixed types. See bit-field details.	0x00000000	Ch 8 Interrupt Enable (receiver).
PL_1_IDR	0x000005001C	32	mixedMixed types. See bit-field details.	0x00000000	Ch 8 Interrupt Disable (receiver).
PL_2_TRIG	0x0000060000	32	mixedMixed types. See bit-field details.	0x00000000	Ch 9 Interrupt Trigger (sender). Default PL 2.
PL_2_OBS	0x0000060004	32	roRead-only	0x00000000	Ch 9 Interrupt Observation (sender).
PL_2_ISR	0x0000060010	32	mixedMixed types. See bit-field details.	0x00000000	Ch 9 Interrupt Status and Clear (receiver). Default PL 2.
PL_2_IMR	0x0000060014	32	roRead-only	0x0F0F0301	Ch 9 Interrupt Mask (receiver).
PL_2_IER	0x0000060018	32	mixedMixed types. See bit-field details.	0x00000000	Ch 9 Interrupt Enable (receiver).
PL_2_IDR	0x000006001C	32	mixedMixed types. See bit-field details.	0x00000000	Ch 9 Interrupt Disable (receiver).
PL_3_TRIG	0x0000070000	32	mixedMixed types. See bit-field details.	0x00000000	Ch 10 Interrupt Trigger (sender). Default PL 3.
PL_3_OBS	0x0000070004	32	roRead-only	0x00000000	Ch 10 Interrupt Observation (sender).
PL_3_ISR	0x0000070010	32	mixedMixed types. See bit-field details.	0x00000000	Ch 10 Interrupt Status and Clear (receiver). Default PL 3.
PL_3_IMR	0x0000070014	32	roRead-only	0x0F0F0301	Ch 10 Interrupt Mask (receiver).
PL_3_IER	0x0000070018	32	mixedMixed types. See bit-field details.	0x00000000	Ch 10 Interrupt Enable (receiver).
PL_3_IDR	0x000007001C	32	mixedMixed types. See bit-field details.	0x00000000	Ch 10 Interrupt Disable (receiver).
IPI_CTRL	0x0000080000	32	rwNormal read/write	0x00000000	IPI Controller Error Signal Control.
IPI_ISR	0x0000080010	32	mixedMixed types. See bit-field details.	0x00000000	IPI Controller Interrupt Status and Clear.
IPI_IMR	0x0000080014	32	roRead-only	0x00000001	IPI Controller Interrupt Mask.
IPI_IER	0x0000080018	32	mixedMixed types. See bit-field details.	0x00000000	IPI Controller Interrupt Enable.
SAFETY_CHK	0x0000080030	32	rwNormal read/write	0x00000000	Scratch register for interconnect data path checking
IPI_IDR	0x00000C001C	32	mixedMixed types. See bit-field details.	0x00000000	IPI Controller Interrupt Disable.