PMCFGR (SMMU500) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID: UG1087
Release Date: 2024-03-13
Revision: 1.10

PMCFGR (SMMU500) Register Description

Register Name	PMCFGR
Offset Address	0x0000003E00
Absolute Address	0x00FD803E00 (SMMU_GPV)
Width	32
Type	roRead-only
Reset Value	0x05011F17
Description	Performance Monitor Configuration register containss PMU specific configuration data.

PMCFGR (SMMU500) Register Bit-Field Summary

Field Name	Bits	Type	Reset Value	Description
NCG	31:24	roRead-only	0x5	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
UEN	19	roRead-only	0x0	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
EX	16	roRead-only	0x1	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
CCD	15	roRead-only	0x0	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
CC	14	roRead-only	0x0	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
SIZE	13:8	roRead-only	0x1F	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
N	7:0	roRead-only	0x17	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details