GDMA_RAM (FPD_SLCR) Register - UG1087

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2025-06-20
Revision
1.11

GDMA_RAM (FPD_SLCR) Register Description

Register NameGDMA_RAM
Offset Address0x0000003010
Absolute Address 0x00FD613010 (FPD_SLCR)
Width16
TypemixedMixed types. See bit-field details.
Reset Value0x00003B3B
DescriptionRAM control register

GDMA_RAM (FPD_SLCR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved15razRead as zero0x0RESERVED. Return 0 when read. Writes ignored.
Reserved14:12rwNormal read/write0x3Reserved
Reserved11rwNormal read/write0x1Reserved
Reserved10:8rwNormal read/write0x3Reserved
Reserved 7rwNormal read/write0x0RESERVED. Return 0 when read. Writes ignored.
Reserved 6:4rwNormal read/write0x3Reserved
Reserved 3rwNormal read/write0x1Reserved
Reserved 2:0rwNormal read/write0x3Reserved