reg_blocksize (SDIO) Register - UG1087

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

reg_blocksize (SDIO) Register Description

Register Namereg_blocksize
Offset Address0x0000000004
Absolute Address 0x00FF160004 (SD0)
0x00FF170004 (SD1)
Width16
TyperwNormal read/write
Reset Value0x00000000
DescriptionConfigure the Number of Bytes in a Data Block.

reg_blocksize (SDIO) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
sdma_bufboundary14:12rwNormal read/write0x0Write the size of the contiguous DMA buffer in the system memory.
The System Address register is updated at every system boundary during the DMA transfer
The DMA transfer waits at the every boundary specified by these fields and the SDIO controller generates the DMA interrupt to request the controller to update the System Address register.
This function is active when the [DMA Enable] bit in the Transfer Mode register is set = 1.
000b: 4KB
001b: 8KB
010b: 16KB
011b: 32KB
100b: 64KB
101b: 128KB
110b: 256KB
111b: 512KB
xfer_blocksize11:0rwNormal read/write0x0Block size for data transfers for CMD17, CMD18, CMD24, CMD25 and CMD53. Read-only. Valid if no transaction is executing (i.e after a transaction has stopped).
0000h: No data transfer.
0001h: 1 byte
0002h: 2 bytes
0003h: 3 bytes
..
0200h: 512 bytes
..
0800h: 2048 bytes (maximum block size)